Ratioless mos sense amplifier

ABSTRACT

A sense amplifier for sensing stored information in a memory system particularly of the integrated circuit type wherein a cross-coupled symmetrical sense amplifier is operated to provide ratioless operation. The invention further utilizes a crosscoupled discriminator to provide improved signal detection which, in conjunction with the ratioless differential amplifier with gated conditional feedback, provides a significant reduction in power, higher operating speed and a reduction in required chip area since minimum geometry devices may be utilized.

United States Patent [191 Lindell Sept. 24, 1974 RATIOLESS MOS SENSEAMPLIFIER [75] Inventor: Edward Lindell, Long Beach, Calif.

[73] Assignee: Lockheed Electronics Company,

Inc., Plainfield, NJ.

22 Filed: Feb. 5, 1973 21 Appl. No.: 329,644

DUMMY szusums (A) I Primary ExaminerHerman Karl Saalbach AssistantExaminer-James B. Mullins Attorney, Agent, or FirmBilly G. Corber;Albert K. Geer [5 7] ABSTRACT A sense amplifier for sensing storedinformation in a memory system particularly of the integrated circuittype wherein a cross-coupled symmetrical sense amplifier is operated toprovide ratioless operation. The invention further utilizes across-coupled discriminator to provide improved signal detection which,in conjunction with the ratioless differential amplifier with gatedconditional feedback, provides a significant reduction in power, higheroperating speed and a reduction in required chip area since minimumgeometry devices may be utilized.

6 Claims, 4 Drawing Figures I sense use (a) I NODE/ 2005 A n i i 02 "A"ROW SELECT "a"-Row SELECT 'l mamoav ceu.

nenomr czu. T

EU REAO lo l-* fllwRITE 'i 0",

narrow (A) Qu 0,, DATA-OU1'(B) nun m 0-] 0,, 0m Q Q" ]o DATA-IN PATENIESEP2413Z4 CL-OCK PHASES FCUR PHASE CLOCKS Fmjz RATIOLESS MOS SENSEAMPLIFIER sense amplifier for integrated circuit capacitance-type memorysystems.

The Prior Art In the metal oxide semiconductor field effect transistor(MOS FET) art, generally one FET is the active device and a second FETacts as a load device. Since the resistance of an MOS structure is afunction of the source-to-gate bias and channel geometry, it isindependent of source-to-drain potential in the saturation region. Thus,an MOS device can be used as a fixed or variable resistor, with theamount of resistance being controlled by the source-to-gate bias.Accordingly, in the usual manner of operation, performance is limited bythe ratio of R, E R i.e. the output depends upon the ratio of theresistance of the active device to that of the load device.

Ratioless operation occurs where the load device and active device arenot on simultaneously, i.e., when the active device is on, the loaddevice is off. An excellent discussion MOSFET Memory Circuits by LewisM. Terman, is found in the Proceedings of the IEEE, Vol.

59, No. 7, July 1971, pages 1044-1058. See also References (7) and ofthe foregoing article. For transient analysis see Transient Analysis ofFour- Phase MOS Switching Circuits by Yao Ting Yen, IEEE Journal ofSolid State Circuits, Vol. SC-3, No. 1, March 1968, pages l-5.

In an article entitled Storage Array and Sense/Refresh Circuit forSingle-Transistor Memory Cells by Stein, Sibling & Doering, 1972 IEEEInternational Solid-State Circuits Conference, pages 56 and 57, there isdiscussed a MOSFET sense amplifier. However, analysis indicates that thedescribed sense amplifier has a relatively high power dissipation as aresult of the ratio type circuits used. In addition, the active devicesused must be larger to provide the required gain and sensitivity.

The present invention improves sense amplifier operation by utilizingthree or more clock phases and a ratioless amplifier technique such thatthe active FET device and the load device are not on simultaneously.When the ratioless sense amplifier is used in conjunction with a crosscoupled discriminator greatly improved sensing is realized.

Accordingly, it is a primary object of the present invention to providea sense amplifier utilizing ratioless techniques.

A further object of the invention is to provide a ratioless senseamplifier in conjunction with a cross coupled discriminator to obtaingreater sensitivity, a reduction in power, higher operating speed and areduction in required area since minimum geometry devices may beutilized.

A further object of the invention is to provide a MOSF ET senseamplifier which improves operation and eliminates one or moredisadvantages of the prior art.

These and other various objects will become more apparent from thefollowing detailed description when taken with the accompanyingdrawings, in which:

FIG. '1 is a preferred embodiment of a ratioless MOS- FET senseamplifier utilizing the present invention;

FIG. 2 is a timing diagram showing the relationship of the clock pulsesin connection with FIG. I.

FIG. 3 is a second embodiment of a MOSFET sense amplifier in accordancewith the invention; and

FIG. 4 is a timing diagram showing the relationships of the clock pulsein connection with FIG. 3.

In the following description, the MOSFET technology is considered to bewell understood, and reference to standard texts and handbooks should bemade for a detailed consideration of MOSFETs. For example, the devicesexplained herein, while illustrated by greatly simplified symbols inFIGS. 1 and 3, are understood to have the conventional source and drainterminals, separated by the substrate, over which lies the gate metal.

' (A) and sense-line (B)), it is understood that the invention isapplicable to a sense amplifier which utilizes a plurality ofsense-lines per sense amplifier in accordance with conventionaltechnology. Sense-line (A) is connected to a memory cell via A rowselect 0 while sense-line (B) is connected to a memory cell via B rowselect O Sense-line (A), commonly referred to hereinafter as Node A, isconnected to ground through Q and Q and sense-line B (Node B) isconnected to ground through 0 and 0,. Node A is connected to clocksource (1), through Q and a diode connected FET D and Node B isconnected to clock source 45, through Q and diode D Node A is likewiseconnected to clock source (b through Q and diode D and Node B isconnected to 4); through Q and diode D Considering the lower part ofFIG. 1, for a read operation, Node A (or B) is read during (p -Read by Q(or Q and for a write operation, Node A (or B) is connected to groundthrough Q and O (or O and Q during qb 'Write. Node A is also connectedthrough Q to an intermediate voltage, say (+5V), and Node B is connectedto the same voltage through Q during (in.

Now considering the operation of FIG. 1 and with reference to the timingdiagram of FIG. 2, the sense amplifier operation is divided into twotime periods: q), and During (b the gates of load devices Q and Q areprecharged through diodes D and D i.e., Q and Q are enabled.Simultaneously, sense-lines (A) and (B) are clamped to the intermediatevoltage (about +5 volts) when 0 and Q are gated on during (1),. Dummycell transistors Q and Q are also gated on during so that both dummycells (B and A) are precharged to the balance (or intermediate voltage.Thus, clock phase 4), is used to precharge capacitance at all nodes ofthe amplifier to predetermined potentials.

Activation of the sense amplifier and memory storage cells isaccomplished during clock phase It will be noted that the 5 clock pulseis applied to diodes D and D and to the gates of Q Q and Q14.

During this initial time interval (4) FIG. 2), the following devices areconducting O,-Q -Q -D and Q -Q O -D (recalling that the gates of Q and Qwere precharged during (1),). Balanced is maintained until the selectedrow bus (A or B) reaches a voltage high enough to turn on the selectedcell transistor 22 or 23. At that point in time, a current unbalance isestablished which is detected by the amplifier and the regenerativecycle is initiated. A ratio condition exists until (V -V 5 V1(threshold) of Q6 01 (VB'-VA) S VT of Q5. The onset of conduction in Qor 0 bleeds off the charge from the gate of or 0,, respectively, andestablishes the required conditions for ratioless operation.

For example, let it be assumed that a one signal was read ontosense-line A by selected transistor Q and Node A rises. This rise isapplied to the gates of Q (amplifier) and Q (discriminator). Thus, whenNode A is a one (say +5.5 or +6 volts), the following transistorsconduct throughout clock phase (1) Q Q Q Q and diode D Transistor Qdrains the gate of Q and transistor Q grounds Node B through QTherefore, transistors 0,, Q Q and diode D are cut off by virtue of thepotentials established at their gate nodes. At the completion of clockphase sense-line (A) will be charged to about +10 or +11 volts andsense-line (B) will be charged to zero (0) volts. If a zero signal hadbeen read on sense-line (A), all devices within the sense amplifierwould reverse their respective roles and sense-line (A) would be chargedto zero volts, while sense-line (B) would be charged to (+10 or +1 1'volts). Thus, the sense amplifier is completely symmetrical, can acceptread signals on the order of 100 millivolts (MV) and will amplify andcharge the selected memory cell to +10 or +11 volts or zero volts,depending upon the information originally stored. Transistors Q anddiodes D and D provide the means for turning on" the amplifier duringand maintaining it in the off" state during all other times including(1),, so that it consumes no power in the off state and does notinterfere with the precharging of the sense-lines during (1),.

Data is transferred to a data-out buffer via transistor Q (or Q duringclock phase (15 and Read (da Read). The Read signal is generated bycolumn decoder circuits which are not shown in the accompanyingdrawings.

Operation of the sense amplifier during a write cycle is similar to thatdescribed above, except that transistor Q and Q are gated on by thecolumn decoder during clock phase (b and Write (qb -write). Thus, if aone is to be written into the cell connected to senseline (A) viatransistor Q transistor Q11 would be turned on, thus clamping sense-line(B) to zero volts.

, Sensing the current unbalance established, the sense to zero volts andthe memory cell would be charged to a zero condition. In this case dummycell A is charged to (+10 or +1 1) volts since it is connected tosense-line (B) via transistor Q The dummy cell is always charged to theopposite state of the selected cell in both read and write cycleoperations. Thus, if the memory cell stores a one," the dummy cell willstore a zero and vice versa. The state of the dummy cell is of noconsequence since it is charged to an intermediate voltage (say +5volts) at the beginning of every memory cycle (4),). The sole purpose ofthe memory cell is to maintain an impedance match between senselines (A)and (B) during clock phase (15 It is believed apparent that additionalmemory cells may be connected in parallel to that shown and having a rowselect transistor corresponding to Q or Q Referring now to FIG. 3, asecond embodiment of the invention will be described. In this case,similar reference characters are used to designate corresponding devicesas previously described. Thus, transistors Q and Q are the senseamplifier, Q and Q the crosscoupled discriminator, Q and Q the loaddevices, etc. Q is now replaced by Q and Q because of the rearrangementof the sense amplifier and discriminator. It is also to be noted thatthe sense amplifierdiscriminator is within the broken lines, with thememory select circuits on the left and the Read/Write logic on theright. Also referring to FIG. 4, the timing diagram utilizes four clockphases. The dummy cells have been omitted for purposes of clarity.Diodes D and D, have been added, as explained hereinafter.

Considering now FIGS. 3 and 4 during clock phase (15 lines A and B(Nodes A and B) are balanced and returned to ground or zero volts via Q-Q in lieu of to an intermediate voltage, as in FIG. 1. The gates of Qand Q, are charged via diodes D and D Also, diodes D and D balance theconnection between Q -Q to that between Q.=.-Q6.

The memory cell is read during 1)2, along with the dummy cell which hasbeen omitted in this Figure. Q conducts during zb Read, charging thegates of Q and Q Assuming a one has been read from a memory cell, say bySelect 1A, onto sense-line (A), Le. S- L(A), Node A rises toward the onevalue or about +2 to +3 volts. This voltage is applied to the gates oftransistors Q and Q The unbalance is detected; Q conducts via O toreduce Node B to zero; Q6 conducts via Q, to reduce Node D to zero,discharging the gate of 0,. As the (15;, clock rises, current through Qand Q varies proportionally to their gate voltages established during(1) or, in other words, inversely to the readout on the sense-lines,i.e., the voltage at the gates of Q and Q If (V, -V 5 V a ratiocondition will be present during the time required to raise (V -V V If aone has been read (Node A is High, resulting in a high at Node C), theselected digit line (Select A Read/Write Logic) is raised to its fullvalue (V,, 212 volts); zero results in a value of (V, s 1 volt). Aftersufficient time has elapsed to guarantee regeneration, the memory wordline is dropped.

Phase four ((1) is used to restore an intermediate value one into thedummy cell (which is not shown in this Figure). At the end of 1b., thedummy word line is dropped, thus completing a read cycle.

A write operation has similar time phases, i.e., (l) precharge, (2) loaddata and (3) regenerate memory cell and restore dummy cell.

All digit lines are restored to zero volts and the gates of Q and Q, areprecharged during 4),, as before. During 'Write, applied to Q the datais gated onto the gate of Q; or Q via Q -Q or 0 -0 5 and select A or B,respectively, while the discriminator and amplifier sections aredisabled. Selection of the selected word line (and dummy word line) arealso accomplished during 4J Regeneration and restore operations arecompleted in identical fashion as described for a read operation withthe exception that the memory cell (and dummy cell) are regeneratedduring (1) and therefore 4)., is not required in a write cycle. Forexample, consider a one to be written into a memory cell on line A; thedata is gated through Q ,-Q during -Write on Q and raises Node C (gateof 0 During Q diode D and Q conduct, raising Node A, whereupon selectionof the desired word line and Select 1A, 2A, etc. charges the desiredmemory cell.

Thus, in both FIGS. 1 and 3 the over-all operation is essentially thesame. For example, let it be assumed that Node A (select line A) is aone, i.e. High; after the initial balance is over and the unbalance isdetected, the following summarizes the ratioless operation:

FIG. 1:

Node A one Q conducts, Q is off Q conducts, the gate of Q, is dischargedQ is off, conducts.

Thus, with O off and Q conducting, the result is ratioless.

FIG. 3:

Node A one Q conducts, Q. is off Q conducts, the gate of O is dischargedQ is off, Q conducts.

Thus, likewise, with 0 off and Q conducting, the result is ratiolessoperation.

What is claimed is:

1. A ratioless MOS sense amplifier comprising: a plurality of memorycells; at least a pair of sense-lines, each of said pair being connectedto a group of said memory cells; means for selecting a memory cell andtransferring the cell information onto oneof said senselines; across-coupled amplifier pair connected to said sense-lines; a loaddevice for each of said amplifier pair; a cross-coupled discriminatorconnected to said sense-line and to said amplifier; means responsive toa first clock interval for enabling said load devices; further meansresponsive to said first clock interval for clamping the sense-lines toa predetermined level; means responsive to a second clock interval forinitiating current flow in the amplifier and load devices,

whereby an unbalance is created by the memory cell information on thesense line; means including the amplifier and discriminator fordetecting the unbalance and raising the selected line to a predeterminedlevel; means for transferring the sense-line information to an output;and means for writing information into a selected cell.

2. A ratioless MOS sense amplifier as defined by claim 1, wherein theamplifier pair is of the MOSFET type and having the drains and gatescross-coupled.

3. A ratioless MOS sense amplifier as defined by claim 1, wherein theload devices are of the MOSFET type, the gates of which are prechargedduring the first clock interval.

4. A ratioless sense amplifier of claim 1 which is of the MOSFET type,wherein the amplifier consists of at least a pair of MOSFET devicesconnected individually to at least one sense-line, each of said deviceshaving its drain coupled to the gate of the other device, whereby anunbalance in the sense-lines is detected, and one of said devicesconducts and the other is cut off.

5. A ratioless sense amplifier as defined by claim 4, wherein eachamplifier includes a MOSFET load device, and means responsive to theunbalance of the sense-lines for turning off the load device associatedwith the conducting MOSFET amplifier and turning on the load deviceassociated with the nonconducting MOSFET amplifier.

6. A ratioless sense amplifier as defined by claim 5, wherein thelast-named means includes a discriminator responsive to the unbalancefor controlling the load de-

1. A ratioless MOS sense amplifier comprising: a plurality of memorycells; at least a pair of sense-lines, each of said pair being connectedto a group of said memory cells; means for selecting a memory cell andtransferring the cell information onto one of said sense-lines; across-coupled amplifier pair connected to said sense-lines; a loaddevice for each of said amplifier pair; a cross-coupled discriminatorconnected to said sense-line and to said amplifier; means responsive toa first clock interval for enabling said load devices; further meansresponsive to said first clock interval for clamping the senselines to apredetermined level; means responsive to a second clock interval forinitiating current flow in the amplifier and load devices, whereby anunbalance is created by the memory cell information on the sense line;means including the amplifier and discriminator for detecting theunbalance and raising the selected line to a predetermined level; meansfor transferring the sense-line information to an output; and means forwriting information into a selected cell.
 2. A ratioless MOS senseamplifier as defined by claim 1, wherein the amplifier pair is of theMOSFET type and having the drains and gates cross-coupled.
 3. Aratioless MOS sense amplifier as defined by claim 1, wherein the loaddevices are of the MOSFET type, the gates of which are precharged duringthe first clock interval.
 4. A ratioless sense amplifier of claim 1which is of the MOSFET type, wherein the amplifier consists of at leasta pair of MOSFET devices connected individually to at least onesense-line, each of said devices having its drain coupled to the gate ofthe other device, whereby an unbalance in the sense-lines is detected,and one of said devices cOnducts and the other is cut off.
 5. Aratioless sense amplifier as defined by claim 4, wherein each amplifierincludes a MOSFET load device, and means responsive to the unbalance ofthe sense-lines for turning off the load device associated with theconducting MOSFET amplifier and turning on the load device associatedwith the nonconducting MOSFET amplifier.
 6. A ratioless sense amplifieras defined by claim 5, wherein the last-named means includes adiscriminator responsive to the unbalance for controlling the loaddevices.